brmlab

User Tools

Site Tools

You are here: Hackerspace Prague » Projects » Ledum
project:ledum:start

Differences

This shows you the differences between two versions of the page.

Link to this comparison view

Both sides previous revisionPrevious revision
Next revision		Previous revision
project:ledum:start [2025/04/25 13:08] – [Streaming Setup in Brmlab] joeproject:ledum:start [2026/08/20 17:29] (current) – joe
Line 4: Line 4:
 name=Ledum| name=Ledum|
 image=ledum:320px-ledum_palustre_bluehend.jpg| image=ledum:320px-ledum_palustre_bluehend.jpg|
-sw=FIXME| +sw=to be determined but open| 
-hw=FIXME|+hw=to be determined but open|
 founder=[[user:yokotashi]]| founder=[[user:yokotashi]]|
 interested=[[user:abyssal]]\\ [[user:bluebear]]\\ [[user:ccx]]\\ [[user:hexo]]\\ [[user:joe]]\\ [[user:prilezitostnypetr]]\\ [[user:rainbof]]\\ [[user:sachy]]\\ [[user:santiago]]\\ [[user:tma]]\\ interested=[[user:abyssal]]\\ [[user:bluebear]]\\ [[user:ccx]]\\ [[user:hexo]]\\ [[user:joe]]\\ [[user:prilezitostnypetr]]\\ [[user:rainbof]]\\ [[user:sachy]]\\ [[user:santiago]]\\ [[user:tma]]\\
Line 12: Line 12:
 }} }}
  
-This project aims to design and develop a new central processing unit (CPU) with a primary focus on //correctness// and //object capabilities.// The design will prioritize formal verification techniques, ensuring the CPU’s functional correctness while introducing innovative approaches to resource management using object capabilities for improved security, efficiency, and modularity. +---- dataentry hidden ---- 
 +name: Ledum 
 +status: active 
 +image: {{:project:ledum:320px-ledum_palustre_bluehend.jpg}} 
 +----
  
 +//Traveling at night is neither faster, nor safer. That's why we do it. (Christopher Illopoly, Cultist Simulator)//
  
-===== Project Objectives =====+This project aims to design and develop a **central processing unit** (CPU) from the ground up, with all circuitry, instruction set, and ways of communication with peripherals devised completely by us. Ideally, at least one of the resulting designs should be so simple that it could be produced in silicon with primitive, 1980-style lithography. If this succeeds, we can advance to more sophisticated designs.
  
-  - **Achieve High Correctness in Design:** +===== Released Repositories =====
-    * Use formal methods, simulation, and rigorous testing to verify that the CPU’s architecture is functionally correct. +
-    * Ensure that the CPU meets or exceeds industry standards for reliability and precision. +
-  - **Implement Object Capabilities Model:** +
-    * Integrate an object capabilities model into the CPU’s architecture to allow fine-grained, secure management of memory and I/O resources. +
-    * Ensure that resource access control is embedded at the hardware level to improve security by default. +
-  - **Enable Scalable Security Mechanisms:** +
-    * Design the CPU with scalable security features, leveraging capabilities to prevent unauthorized access and misuse of system resources. +
-    * Provide users with the flexibility to define and manage their own access control policies through object capabilities. +
-  - **Optimize Performance:** +
-    * Ensure that the CPU achieves optimal performance in terms of throughput, latency, and power consumption, without compromising correctness or security. +
-    * Ensure, that the CPU architecture can be parallelized to achieve IPC>1 including OoO execution, although to do so isn't primary objective.  +
-    * Balance hardware features for high-performance tasks with robust security measures for sensitive operations. +
-  - **Establish Robust Ecosystem Support:** +
-    * Develop comprehensive software toolchains and drivers to support the object capability model. +
-    * Collaborate with industry partners to ensure broad compatibility with existing operating systems and applications.+
  
 +  * [[https://ledum.codeberg.page/ledum-definers/|Ledum Definers (DSL)]]
 +  * [[https://ledum.codeberg.page/ledum-bb68/|BB68 ISA]]
  
-===== Project Scope =====+===== Project goals and timeline (very approximate) =====
  
-==== In-Scope ====+==== 2024-2027(?): first phase ====
  
-  * **CPU Architecture Design:** Define instruction sets, pipeline architecture, memory hierarchy, and integration of object capabilities. +    * a simple, but functional, 100% open source 16-bit CPU with an original instruction set 
-  * **Formal Verification:** Apply formal methods to mathematically prove the correctness of critical parts of the architecture. +    * here we want to learn all the needed technology for designing a complex circuitry needed for a (still simple) CPU 
-  * **Security & Resource Management:** Implement object capabilities as a mechanism to control access to system resources. +    * the CPU itself, if successful, should also be a teaching tool for showing how to do these things 
-  * **Prototyping and Simulation:** Build prototypes and simulate the architecture to validate design decisions. +    * technically inspired by the most famous old CPUs: 6502, Z80, Motorola 68000 
-  * **Performance Evaluation:** Benchmark the new CPU's performance across several applications to assess trade-offs between correctness, performance, and security. +    * status: 
-  * **Software Toolchain Development:** Develop and release supporting software tools, such as compilers, debuggers, and simulators, that work with the new object capability model.+        * tooling for building an instruction set (by [[user:joe]]) are complete, namely: 
 +             * generator of instruction structure and bit layout 
 +             * assembler and disassembler 
 +             * emulator 
 +        * instruction set is complete (by [[user:bluebear]]) - codename "BB68" 
 +        * hardware capabilities and high-level schematics are complete (by [[user:tma]]) 
 +        * Verilog sources for the detailed hardware are in progress (by [[user:tma]]) 
 +        * basic BIOS-like (KERNAL for C64 afficionados) is in progress (by [[user:joe]]) 
 +        * compiler for higher but still low-level C-language is being prepared (by [[user:bluebear]])
  
-==== Out of Scope ====+==== 2028(?): second phase ====
  
-  * Development of end-user software applications or operating systems. +    * according to how successful the first design is, we may decide to build a whole non-testing computer around it, or use the experience to devise a larger, more sophisticated CPU with properties which are interesting for modern software design: 
-  * Manufacturing of physical CPU chips (to be handled post-design phase). +        * scalable, capabilities-based security model 
-  * Integration into mass-market consumer devices (focus will be on specialized, high-assurance markets initially).+        * features for comfortable coding in assembly for speed sensitive routines (to be fleshed out later - [[user:yokotashi]]'s domain) 
 +            * about 64 registers with support for tagging and hardware types (secure pointer arithmetic) 
 +            * instructions allowing both high code density (variable length) and fast execution (more complex decoding but better performance) 
 +            * in-CPU circuitry for more sophisticated calculations, like divisor, hasher... 
 +            * fast calls to the kernel 
 +        * performance optimizations known in modern CPUs 
 +            * parallelizability, IPC>1 including OoO execution 
 +            * configurable balance between throughput, latency, and power consumption (without compromising security)
  
 ===== Workshops ===== ===== Workshops =====
  
-As a part of our efforts, we have realized that different members of the team have different experience with various scientific and engineering fields and it would be very helpful to ensure that everyone has some basic understanding of all required topics. The workshops typically take place during the working group's regular meetings on Thursdays (see [[event:start]]).+As a part of our efforts, we have realized that different members of the team have different experience with various scientific and engineering fields and it would be very helpful to ensure that everyone has some basic understanding of all required topics. The workshops typically take place during the working group's regular meetings on **Thursdays** (see [[event:start]]).
  
 If there is enough interest, we are streaming the workshops online using [[https://meet.jit.si/ledum-wg-meetup]]. We are also trying to get our A/V streaming and editing skills to a level that allows for publishing the recordings of the workshops. Any help with such endeavor would be more than welcome. If there is enough interest, we are streaming the workshops online using [[https://meet.jit.si/ledum-wg-meetup]]. We are also trying to get our A/V streaming and editing skills to a level that allows for publishing the recordings of the workshops. Any help with such endeavor would be more than welcome.
  
-==== Streaming Setup in Brmlab ==== +==== Past Workshops and Sessions ====
- +
-The public laptop available in the social room, clearly labeled "Brmlab", has some rudimentary setup for online streaming of Ledum Working Group Meetings. The online session can be setup as follows: +
- +
-  - Locate the aforementioned laptop. +
-  - Find its power supply adapter. +
-  - Put the laptop on a table near the pack of cables hanging down from the ceiling roughly in the middle of the room. +
-  - Connect the power supply adapter to 230V socket and to the laptop. +
-  - Power up the laptop by pressing the power button located just left of the delete key which is in the top right corner of the keyboard and double-check it is not running only on the battery. +
-  - Connect a mouse to the laptop - it is really needed for any actual directing of the session. +
-  - Go to the audio mixing table - by the time of this writing, it is located by the 3rd window pair counting from the entrance +
-  - At the table, search for and pick up: +
-    * red/black USB device for capturing HDMI output  +
-    * blue USB-A to USB-A USB 3.0 cable +
-    * (probably black) HDMI cable of sufficient length (2m should be OK) +
-  - Get back to the laptop and connect the HDMI capture device to the remaining USB-A port of the laptop. +
-  - Start the Chromium browser and load the meeting URL (see above). +
-  - Grab the HDMI cable going from the projector just under the ceiling and connect it to the integrated HDMI port on the right hand side of the laptop (next to the power supply connector). +
-  - Power up the projector using the "Optoma" remote clipped to the pack of cables slightly above the table. You need to press the red power button in the top left corner twice and the red light on the projector should change to blue. +
-  - Ensure the system is configured to use the external projector as secondary / separate screen. +
-  - Start OBS Studio (it is installed). +
-  - If it asks for the permission to share a screen window, check it is the Chromium browser window you have just opened and allow sharing. +
-  - In the "Scene Collections" menu at the top of OBS Studio's window, check whether "LedumMeeting" is selected and select it if it is not. +
-  - Select the "Default" scene in the lower left corner of the window. +
-  - Ensure the laptop's internal camera located just above its display has its cap open. +
-  - In the sources list right to the scene selection of the previous step, check and ensure: +
-    * The "JitsiWindow" source shares the Chromium browser window opened earlier. +
-    * The "SpeakerCamera" displays the image from the front camera facing the director of the session (that is typically you). +
-    * The "HDMICapture" properly sees whatever you connect to it (typically use another laptop to double-check). +
-  - Now that everything is ready, click the "Start Virtual Camera" button in the lower right corner (fourth from the bottom). You may need to enter the password "brmbrm". +
-  - Go back to Chromium browser window and select the newly created "OBS Camera" as the primary video source for the Jitsi meeting. +
-  - Go back to OBS Studio and select the "Intro" scene and you are ready to go.  +
- +
-==== Past Workshops ====+
  
   * 2024-10-10 16:00 [[user:tma]] - Verilog I: Introduction to Verilog (CZ)   * 2024-10-10 16:00 [[user:tma]] - Verilog I: Introduction to Verilog (CZ)
Line 103: Line 77:
   * 2024-12-12 16:00 [[user:ccx]] -- History of Capability Systems I (CZ)   * 2024-12-12 16:00 [[user:ccx]] -- History of Capability Systems I (CZ)
   * 2025-01-09 17:00 [[user:hexo]] -- Adders and Multipliers (CZ/SK)   * 2025-01-09 17:00 [[user:hexo]] -- Adders and Multipliers (CZ/SK)
 +  * 2025-01-23 16:00 [[user:tma]] -- Wallace Tree (CZ)
 +  * 2026-06-05 16:00 [[user:tma]] -- Capabilities Discussion (CZ)
 +  * 2026-06-12 16:00 [[user:ccx]] -- Capabilities Discussion (CZ)
 +  * 2026-06-19 16:00 [[user:joe]] -- Capabilities Discussion (CZ)
 +  * 2026-04-23 16:00 [[user:joe]] -- Graphical Output, BIOS, Interrupts (CZ)
 +  * 2026-04-30 16:00 [[user:joe]] -- VGA monitor simulation, Forth, ABI (CZ)
 +  * 2026-07-09 16:00 [[user:joe]] -- Releases: ledum-definers, BB68 (CZ)
  
-==== Planned ==== 
- 
- 
-===== Design Topics ===== 
-==== ISA Description ==== 
-Warning: This part may change wildly at this stage. 
- 
-=== Registers === 
-   * 64 GPR  
-   * upto 64 PTR (Pointer registers) 
-   * special registers (CS:IP and several configuration registers probably) 
-   *- No flag register (flags are going either to another GPR or to a special 4-bits adjacent to every GPR), this should help future with parallelization 
- 
-=== Pointers === 
-   * Fat Pointers supported and tested by HW 
-   * Ultra Fat Pointers supported and tested by HW, can't be dereferenced outside the CS stored inside them 
- 
-=== Tagging === 
-   * All RAM and registers is tagged, so ALU knows which type it's operating on and pointer cannot be created freely 
-   * Types: int, uint, float in 4, 8 ... 64 bit lengths fit in vector 64-bit long; Fat pointer, Ultra fat pointer 
- 
-==== Electronic Circuit Design ==== 
- 
-==== Integrated Circuit Design ==== 
- 
-==== Tooling ==== 
- 
-==== Miscellaneous ==== 
 === Things to read === === Things to read ===
-== Optimizations == 
-- Compressed pointers: https://shipilev.net/jvm/anatomy-quarks/23-compressed-references/ 
  
-- Read barriers pro concurent scavenger: https://blog.openj9.org/2019/03/25/concurrent-scavenge-garbage-collection-policy/ + HW support https://www.ibm.com/support/pages/pause-less-garbage-collection-java-ibm-z https://www.ibm.com/docs/en/zos/3.1.0?topic=ixg-ieagsf-guarded-storage-facility-services+==== Optimizations ====
  
-- Chinual: https://tumbleweed.nu/r/lm-3/uv/chinual.html+    * Compressed pointers: https://shipilev.net/jvm/anatomy-quarks/23-compressed-references/ 
 +    * Read barriers pro concurent scavenger: https://blog.openj9.org/2019/03/25/concurrent-scavenge-garbage-collection-policy/ + HW support https://www.ibm.com/support/pages/pause-less-garbage-collection-java-ibm-z https://www.ibm.com/docs/en/zos/3.1.0?topic=ixg-ieagsf-guarded-storage-facility-services 
 +    * Chinual: https://tumbleweed.nu/r/lm-3/uv/chinual.html 
 +    * https://pqnelson.github.io/org-notes/comp-sci/lisp/machine/i/architecture.html
  
-- https://pqnelson.github.io/org-notes/comp-sci/lisp/machine/i/architecture.html +===== Past milestones =====
-===== Current Progress ===== +
- +
-==== Tooling ====+
  
 {{ :project:ledum:rawaketa-l8b-breakout.png?direct&400|}} {{ :project:ledum:rawaketa-l8b-breakout.png?direct&400|}}
Line 153: Line 104:
 <WRAP clear></WRAP> <WRAP clear></WRAP>
  
-~~META: +==== Simulator GUI ====
-status = active +
-&relation firstimage = :project:ledum:320px-ledum_palustre_bluehend.jpg +
-~~+
  
 +{{ :project:ledum:qasireu-lqabec-socm1-gesicht.png?400|}}
  
 +A simple GUI was developed for simulating a SOC written in Verilog.
 +
 +<WRAP clear></WRAP>
  
project/ledum/start.1745586503.txt.gz · Last modified: 2025/04/25 13:08 by joe