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--- project:ledum:start [2025/04/14 23:30] – [Miscellaneous] Learning formattiong of this wiki by trial and error yokotashi
+++ project:ledum:start [2026/07/11 21:50] (current) – Fixed naming "dzoe" -> "joe", added note about "BB68" bluebear
@@ Line 4: / Line 4: @@
 name=Ledum|
 image=ledum:320px-ledum_palustre_bluehend.jpg|
-sw=FIXME|
+sw=to be determined but open|
-hw=FIXME|
+hw=to be determined but open|
 founder=[[user:yokotashi]]|
 interested=[[user:abyssal]]\\ [[user:bluebear]]\\ [[user:ccx]]\\ [[user:hexo]]\\ [[user:joe]]\\ [[user:prilezitostnypetr]]\\ [[user:rainbof]]\\ [[user:sachy]]\\ [[user:santiago]]\\ [[user:tma]]\\
@@ Line 12: / Line 12: @@
 }}
-This project aims to design and develop a new central processing unit (CPU) with a primary focus on //correctness// and //object capabilities.// The design will prioritize formal verification techniques, ensuring the CPU’s functional correctness while introducing innovative approaches to resource management using object capabilities for improved security, efficiency, and modularity.
+---- dataentry project ----
+name: Ledum
+status: active
+image: {{:project:ledum:320px-ledum_palustre_bluehend.jpg}}
+----
+//Traveling at night is neither faster, nor safer. That's why we do it. (Christopher Illopoly, Cultist Simulator)//
-===== Project Objectives =====
+This project aims to design and develop a **central processing unit** (CPU) from the ground up, with all circuitry, instruction set, and ways of communication with peripherals devised completely by us. Ideally, at least one of the resulting designs should be so simple that it could be produced in silicon with primitive, 1980-style lithography. If this succeeds, we can advance to more sophisticated designs.
-  - **Achieve High Correctness in Design:**
+===== Project goals and timeline (very approximate) =====
-    * Use formal methods, simulation, and rigorous testing to verify that the CPU’s architecture is functionally correct.
-    * Ensure that the CPU meets or exceeds industry standards for reliability and precision.
-  - **Implement Object Capabilities Model:**
-    * Integrate an object capabilities model into the CPU’s architecture to allow fine-grained, secure management of memory and I/O resources.
-    * Ensure that resource access control is embedded at the hardware level to improve security by default.
-  - **Enable Scalable Security Mechanisms:**
-    * Design the CPU with scalable security features, leveraging capabilities to prevent unauthorized access and misuse of system resources.
-    * Provide users with the flexibility to define and manage their own access control policies through object capabilities.
-  - **Optimize Performance:**
-    * Ensure that the CPU achieves optimal performance in terms of throughput, latency, and power consumption, without compromising correctness or security.
-    * Ensure, that the CPU architecture can be parallelized to achieve IPC>1 including OoO execution, although to do so isn't primary objective.
-    * Balance hardware features for high-performance tasks with robust security measures for sensitive operations.
-  - **Establish Robust Ecosystem Support:**
-    * Develop comprehensive software toolchains and drivers to support the object capability model.
-    * Collaborate with industry partners to ensure broad compatibility with existing operating systems and applications.
+==== 2024-2027(?): first phase ====
-===== Project Scope =====
+    * a simple, but functional, 100% open source 16-bit CPU with an original instruction set
+    * here we want to learn all the needed technology for designing a complex circuitry needed for a (still simple) CPU
+    * the CPU itself, if successful, should also be a teaching tool for showing how to do these things
+    * technically inspired by the most famous old CPUs: 6502, Z80, Motorola 68000
+    * status:
+        * tooling for building an instruction set (by [[user:joe]]) are complete, namely:
+             * generator of instruction structure and bit layout
+             * assembler and disassembler
+             * emulator
+        * instruction set is complete (by [[user:bluebear]]) - codename "BB68"
+        * hardware capabilities and high-level schematics are complete (by [[user:tma]])
+        * Verilog sources for the detailed hardware are in progress (by [[user:tma]])
+        * basic BIOS-like (KERNAL for C64 afficionados) is in progress (by [[user:joe]])
+        * compiler for higher but still low-level C-language is being prepared (by [[user:bluebear]])
-==== In-Scope ====
+==== 2028(?): second phase ====
-  * **CPU Architecture Design:** Define instruction sets, pipeline architecture, memory hierarchy, and integration of object capabilities.
+    * according to how successful the first design is, we may decide to build a whole non-testing computer around it, or use the experience to devise a larger, more sophisticated CPU with properties which are interesting for modern software design:
-  * **Formal Verification:** Apply formal methods to mathematically prove the correctness of critical parts of the architecture.
+        * scalable, capabilities-based security model
-  * **Security & Resource Management:** Implement object capabilities as a mechanism to control access to system resources.
+        * features for comfortable coding in assembly for speed sensitive routines (to be fleshed out later - [[user:yokotashi]]'s domain)
-  * **Prototyping and Simulation:** Build prototypes and simulate the architecture to validate design decisions.
+            * about 64 registers with support for tagging and hardware types (secure pointer arithmetic)
-  * **Performance Evaluation:** Benchmark the new CPU's performance across several applications to assess trade-offs between correctness, performance, and security.
+            * instructions allowing both high code density (variable length) and fast execution (more complex decoding but better performance)
-  * **Software Toolchain Development:** Develop and release supporting software tools, such as compilers, debuggers, and simulators, that work with the new object capability model.
+            * in-CPU circuitry for more sophisticated calculations, like divisor, hasher...
+            * fast calls to the kernel
-==== Out of Scope ====
+        * performance optimizations known in modern CPUs
+            * parallelizability, IPC>1 including OoO execution
-  * Development of end-user software applications or operating systems.
+            * configurable balance between throughput, latency, and power consumption (without compromising security)
-  * Manufacturing of physical CPU chips (to be handled post-design phase).
-  * Integration into mass-market consumer devices (focus will be on specialized, high-assurance markets initially).
 ===== Workshops =====
-As a part of our efforts, we have realized that different members of the team have different experience with various scientific and engineering fields and it would be very helpful to ensure that everyone has some basic understanding of all required topics. The workshops typically take place during the working group's regular meetings on Thursdays (see [[event:start]]).
+As a part of our efforts, we have realized that different members of the team have different experience with various scientific and engineering fields and it would be very helpful to ensure that everyone has some basic understanding of all required topics. The workshops typically take place during the working group's regular meetings on **Thursdays** (see [[event:start]]).
-If there is enough interest, we are streaming the workshops online using [[https://meet.jit.si/]]. We are also trying to get our A/V streaming and editing skills to a level that allows for publishing the recordings of the workshops. Any help with such endeavor would be more than welcome.
+If there is enough interest, we are streaming the workshops online using [[https://meet.jit.si/ledum-wg-meetup]]. We are also trying to get our A/V streaming and editing skills to a level that allows for publishing the recordings of the workshops. Any help with such endeavor would be more than welcome.
 ==== Past Workshops ====
@@ Line 71: / Line 73: @@
   * 2025-01-09 17:00 [[user:hexo]] -- Adders and Multipliers (CZ/SK)
-==== Planned ====
+=== Things to read ===
+==== Optimizations ====
-===== Design Topics =====
+    * Compressed pointers: https://shipilev.net/jvm/anatomy-quarks/23-compressed-references/
-==== ISA Description ====
+    * Read barriers pro concurent scavenger: https://blog.openj9.org/2019/03/25/concurrent-scavenge-garbage-collection-policy/ + HW support https://www.ibm.com/support/pages/pause-less-garbage-collection-java-ibm-z https://www.ibm.com/docs/en/zos/3.1.0?topic=ixg-ieagsf-guarded-storage-facility-services
-Warning: This part may change wildly at this stage.
+    * Chinual: https://tumbleweed.nu/r/lm-3/uv/chinual.html
+    * https://pqnelson.github.io/org-notes/comp-sci/lisp/machine/i/architecture.html
-=== Registers ===
+===== Past milestones =====
-   * 64 GPR
-   * upto 64 PTR (Pointer registers)
-   * special registers (CS:IP and several configuration registers probably)
-   *- No flag register (flags are going either to another GPR or to a special 4-bits adjacent to every GPR), this should help future with parallelization
-=== Pointers ===
+{{ :project:ledum:rawaketa-l8b-breakout.png?direct&400|}}
-   * Fat Pointers supported and tested by HW
-   * Ultra Fat Pointers supported and tested by HW, can't be dereferenced outside the CS stored inside them
-=== Tagging ===
+{{:project:ledum:rawaketa-l8b-assembler.png?direct&400 |}}
-   * All RAM and registers is tagged, so ALU knows which type it's operating on and pointer cannot be created freely
-   * Types: int, uint, float in 4, 8 ... 64 bit lengths fit in vector 64-bit long; Fat pointer, Ultra fat pointer
-==== Electronic Circuit Design ====
+As a proof-of-concept an assembly language compiler and IDE support was implemented for a very simple Harvard architecture 8-bit CPU. A graphical emulator for the same simple CPU was created as well. The aim of these tooling efforts is to provide a unified framework for creating custom instruction sets including their assemblers and emulators.
-==== Integrated Circuit Design ====
+<WRAP clear></WRAP>
-==== Tooling ====
+==== Simulator GUI ====
-==== Miscellaneous ====
+{{ :project:ledum:qasireu-lqabec-socm1-gesicht.png?400|}}
-=== Things to read ===
-== Optimizations ==
-- Compressed pointers: https://shipilev.net/jvm/anatomy-quarks/23-compressed-references/
-- Read barriers pro concurent scavenger: https://blog.openj9.org/2019/03/25/concurrent-scavenge-garbage-collection-policy/ + HW support https://www.ibm.com/support/pages/pause-less-garbage-collection-java-ibm-z https://www.ibm.com/docs/en/zos/3.1.0?topic=ixg-ieagsf-guarded-storage-facility-services
+A simple GUI was developed for simulating a SOC written in Verilog.
-- Chinual: https://tumbleweed.nu/r/lm-3/uv/chinual.html
-- https://pqnelson.github.io/org-notes/comp-sci/lisp/machine/i/architecture.html
-===== Current Progress =====
-==== Tooling ====
-{{ :project:ledum:rawaketa-l8b-breakout.png?direct&400|}}
-{{:project:ledum:rawaketa-l8b-assembler.png?direct&400 |}}
-As a proof-of-concept an assembly language compiler and IDE support was implemented for a very simple Harvard architecture 8-bit CPU. A graphical emulator for the same simple CPU was created as well. The aim of these tooling efforts is to provide a unified framework for creating custom instruction sets including their assemblers and emulators.
 <WRAP clear></WRAP>