project:ledum:start
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| project:ledum:start [2025/07/03 22:42] – [ISA Description] description of process creator yokotashi | project:ledum:start [2025/07/04 08:58] (current) – asm sachy | ||
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| There may be more process creators. | There may be more process creators. | ||
| The main reason for existence of process creator is possibility to create a child without being able to travel down through it's memory. Process creator will have this ability of course, but it should be small, simple and well audited. | The main reason for existence of process creator is possibility to create a child without being able to travel down through it's memory. Process creator will have this ability of course, but it should be small, simple and well audited. | ||
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| + | ==== Inctructions and assembly ==== | ||
| + | |||
| + | * Fixed-length instructions (64 bit) - decoder simplicity | ||
| + | * Instructions aligned to 64 bit addresses - decoder simplicity | ||
| + | * First 8 b is an opcode | ||
| + | * Macro-instructions (???) | ||
| + | * Single instruction is unrolled into multiple instuctions by instruction decoder and then executed by the CPU as if coded by hand | ||
| + | * Increased code density - things like clearing multiple registers by single "XRM 1,15" (Xor Register - Multiple reg_n, | ||
| + | * Hardcoded in CPU wiring | ||
| + | * Supervisor Call Instructions | ||
| + | * Instruction passed outside of fiber/CPU and result passed back into specified register | ||
| + | * Raw-content register communication only, no way to pass memory | ||
| + | * Things like: | ||
| + | * Get current timestamp from BIOS or whomever | ||
| + | * Power management - tell the motherboard to sleep/turn off | ||
| + | * lowlevel ioctl used by hardware broker task | ||
| + | * VM communication? | ||
| + | * Allow itself being debugged? | ||
| + | * Message passing between fibers and basic services | ||
| + | * Inter-CPU communication (multicore, multisocket) | ||
| + | * Supported instruction set | ||
| + | * Derived from real-life massive applications by statistical analysis of used instructions | ||
| + | * Go along Parret rule that 20 % instructions do 80 % work - optimize that, ignore specialties | ||
| + | * Semaphores instructions | ||
| + | * Compare-swap | ||
| + | * ST0 - Store 0 or set condition code; ST1 - Store 1 or set condition code - if the memory was already non-zero (non-one), soft fail - atomic locking | ||
| + | * Vector processing | ||
| + | * Register treated as a vector of 4/8/16/32b long values | ||
| + | * Inctruction naming convention to be defined | ||
| + | * Hex representation and opcode allocation to be defined | ||
| + | * | ||
| + | |||
| + | |||
| ==== Electronic Circuit Design ==== | ==== Electronic Circuit Design ==== | ||
project/ledum/start.txt · Last modified: 2025/07/04 08:58 by sachy