Table of Contents
Ledum
- name:
- Ledum
- statu:
- active
- image:
- {{:project:ledum:320px-ledum_palustre_bluehend.jpg}}
Traveling at night is neither faster, nor safer. That's why we do it. (Christopher Illopoly, Cultist Simulator)
This project aims to design and develop a central processing unit (CPU) from the ground up, with all circuitry, instruction set, and ways of communication with peripherals devised completely by us. Ideally, at least one of the resulting designs should be so simple that it could be produced in silicon with primitive, 1980-style lithography. If this succeeds, we can advance to more sophisticated designs.
Project goals and timeline (very approximate)
2024-2027(?): first phase
- a simple, but functional, 100% open source 16-bit CPU with an original instruction set
- here we want to learn all the needed technology for designing a complex circuitry needed for a (still simple) CPU
- the CPU itself, if successful, should also be a teaching tool for showing how to do these things
- technically inspired by the most famous old CPUs: 6502, Z80, Motorola 68000
- status:
- tooling for building an instruction set (by joe) are complete, namely:
- generator of instruction structure and bit layout
- assembler and disassembler
- emulator
- instruction set is complete (by bluebear) - codename “BB68”
- hardware capabilities and high-level schematics are complete (by tma)
- Verilog sources for the detailed hardware are in progress (by tma)
- basic BIOS-like (KERNAL for C64 afficionados) is in progress (by joe)
- compiler for higher but still low-level C-language is being prepared (by bluebear)
2028(?): second phase
- according to how successful the first design is, we may decide to build a whole non-testing computer around it, or use the experience to devise a larger, more sophisticated CPU with properties which are interesting for modern software design:
- scalable, capabilities-based security model
- features for comfortable coding in assembly for speed sensitive routines (to be fleshed out later - Yokotashi's domain)
- about 64 registers with support for tagging and hardware types (secure pointer arithmetic)
- instructions allowing both high code density (variable length) and fast execution (more complex decoding but better performance)
- in-CPU circuitry for more sophisticated calculations, like divisor, hasher…
- fast calls to the kernel
- performance optimizations known in modern CPUs
- parallelizability, IPC>1 including OoO execution
- configurable balance between throughput, latency, and power consumption (without compromising security)
Workshops
As a part of our efforts, we have realized that different members of the team have different experience with various scientific and engineering fields and it would be very helpful to ensure that everyone has some basic understanding of all required topics. The workshops typically take place during the working group's regular meetings on Thursdays (see Events).
If there is enough interest, we are streaming the workshops online using https://meet.jit.si/ledum-wg-meetup. We are also trying to get our A/V streaming and editing skills to a level that allows for publishing the recordings of the workshops. Any help with such endeavor would be more than welcome.
Past Workshops
- 2024-10-10 16:00 tma - Verilog I: Introduction to Verilog (CZ)
- 2024-10-24 16:00 tma - Verilog II: Register Bank in Verliog (CZ)
- 2024-10-31 16:00 joe - Lambda Calculus I: Introduction to Lambda Calculus (CZ)
- 2024-11-07 18:00 tma - Verilog III: Advanced Verilog (CZ)
- 2024-11-14 16:00 sachy - Assembler on Mainframes (CZ)
- 2024-11-21 18:00 Yokotashi - Introduction to Electronics (CZ)
- 2024-11-28 16:00 tma - Verilog IV: Testbenches (CZ)
- 2024-12-05 16:00 joe - Lambda Calculus II: Lexical Scoping and Evaluator Implementation (CZ)
- 2024-12-12 16:00 ccx – History of Capability Systems I (CZ)
- 2025-01-09 17:00 hexo – Adders and Multipliers (CZ/SK)
Things to read
Optimizations
- Compressed pointers: https://shipilev.net/jvm/anatomy-quarks/23-compressed-references/
Past milestones
As a proof-of-concept an assembly language compiler and IDE support was implemented for a very simple Harvard architecture 8-bit CPU. A graphical emulator for the same simple CPU was created as well. The aim of these tooling efforts is to provide a unified framework for creating custom instruction sets including their assemblers and emulators.
Simulator GUI
A simple GUI was developed for simulating a SOC written in Verilog.
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